An embodiment relates to the block decoder of a flash memory device and, more particularly, to the block decoder of a flash memory device which is capable of preventing charges from flowing into the channel of an unselected memory block.
Recently, there is an increasing demand for nonvolatile memory devices, which can be electrically programmed and erased, and do not require the refresh function of rewriting data at specific intervals. To develop high-capacity memory devices capable of storing a large amount of data, research is being done on technologies for the high integration of memory devices. Accordingly, active research is being done on flash memory.
Flash memory is mainly classified into NAND-type flash memory and NOR-type flash memory. The NOR-type flash memory has an excellent random access time characteristic because it has memory cells each independently coupled with a bit line and a word line. The NAND-type flash memory is excellent in terms of the degree of integration because it has a plurality of memory cells coupled together in series and so requires only one contact per cell string. For such a reason, the NAND-type structure is mainly used in high-integration flash memory.
In general, a flash memory device requires a block decoder for selecting a memory cell array on a block basis in order to perform program, read, and erase operations for a memory cell.
FIG. 1 is a circuit diagram of a flash memory device illustrating a conventional block decoder, and FIG. 2 shows waveforms of operation signals for controlling an unselected memory block of the conventional block decoder.
The operation of the block decoder for controlling an unselected memory block is described below with reference to FIGS. 1 and 2.
First, a NAND gate ND1 is configured to logically combine pre-decoded address signals XA, XB, XC, and XD and to output a first output signal ADD. A NAND gate ND2 is configured to logically combine the first output signal ADD and a program precharge signal PGMPREb and to output a second output signal CON. Accordingly, when at least one of the address signals XA, XB, XC, and XD is in a low level, the NAND gate ND1 outputs the first output signal ADD of a high level. When at least one of the program precharge signal PGMPREb and the first output signal ADD of the NAND gate ND1 is in a low level, the NAND gate ND2 outputs the second output signal CON of a high level. Here, the address signals XA, XB, XC, and XD correspond to an unselected memory block, and so at least one of the address signals XA, XB, XC, and XD is applied at a low level (e.g., the address signal XA can be applied with a low level). Accordingly, the first output signal ADD of a high level is generated, and the second output signal CON of a high level is generated for a certain period of time in response to the first output signal ADD of a high level and the program precharge signal PGMPREb of a low level. Thus, a NAND gate ND3 generates a third output signal DIS of a low level for a certain period of time in response to the second output signal CON of a high level and an enable signal EN of a high level. Consequently, a discharge unit 40 is in a disable state.
The certain period of time in which the third output signal DIS of a low level is generated is a period in which the output node Q1 of all block decoders of a selected memory block and an unselected memory block is precharged. If the third output signal DIS is applied at a high level during this period, the output node Q1 drops to a ground path, and so a program operation on the selected memory cell block is not properly performed.
Accordingly, the program precharge signal PGMPREb of a low level is applied for the certain period of time in order to secure the precharge period.
However, the program precharge signal PGMPREb of a low level is a global signal, and so it is applied to the block decoders of not only the selected memory block, but also the unselected memory block. Accordingly, the discharge unit 40 makes the source selection line and the drain selection line of the unselected memory block a floating state. If the source selection line and the drain selection line of the unselected memory block become a floating state, a bit line and a common source line rise to a power source voltage (Vcc) level. Accordingly, the source selection line and the drain selection line are boosted and raised to the power source voltage (Vcc) level. Consequently, charges of the bit line and the common source line flow into a cell channel. In this case, when a verification operation starts after the program operation for the selected memory block is finished, the charge flow lowers a voltage of the word line of all the unselected memory blocks to a negative (−) voltage through the coupling effect between the bit line and the word line, and causes the bias of a global word line to flow into the word line of the unselected memory blocks, thereby generating a bias drop phenomenon. Accordingly, the program operation for the selected memory block is not properly performed, resulting in a failed program operation.